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GATE 2020 - Computer Organization and Architecture

This Test will cover complete Computer Organization and Architecture with very important questions, starting off from basics to advanced level.
Q. Consider a CRT display that has a next mode display format of 80 x 25 characters with a 9 x 12 character cell. What is the video buffer RAM for the display to be used in monochrome(1 bit per pixel) graphics mode?
Q. Which of the following is used as storage locations both in the ALU and the control section of a computer?
Q. The ability to temporarily halt the CPU and use this time to send information on buses is called?
Q. If we use 3 bits in the instruction word to indicate if an index register is to be used and if necessary, which one is to be used, then the number of index registers to be used in the machine will be?

Q. Which of the following is not typically found in the status register of a micro processor?
Q. Serial input data of 8085 can be loaded into bit 7 of the accumulator by?
Q. The address range to which I/O chip will respond is?
Q. When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the?
Q. Memory refreshing may be done __________?

Q. Each cell of a station Random Access memory contains?
Q. What is the average Access Time for a Drum rotating at 4000 revolutions per minute?
Q. Comparing the time T1 taken for a single instruction on a pipelined CPU, with time T2 taken on a non-pipelined but identical CPU, we can say that __________?
Q. How many wires are threaded through the cores in a coincident-current core memory?
Q. Which access method is used for obtaining a record from cassette tape?
Q. What is the hit ratio of a cache if a system performs memory access at 30 nanoseconds with the cache and 150 nanoseconds without it? Assume that the each uses 20 nanosecs of memory, choose the closest approximate.

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